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 Features
* All Functions and Channel Selections are Controlled by Serial Bus
RF Part
* * * *
All Oscillators and PLL Integrated IF Converter FM Demodulator RSSI
Low Frequency Part
* * * * *
Asymmetrical Input of Microphone Amplifier Asymmetrical Output of Earpiece Amplifier Compander Power Supply Management Serial Bus
Single-chip Cordless Telephone IC U3600BM
Application
* CT0 Standard * Narrowband Voice and Data Transmitting/Receiving Systems
1. Description
The programmable single-chip multichannel cordless phone IC includes all necessary low frequency parts such as microphone- and earphone amplifier, compander, powersupply management as well as all RF parts such as IF converter, FM demodulator, RSSI, oscillators and PLL. Several gains and mutes in transmit and receive direction are controlled by the serial bus. The compander can be bypassed.
Rev. 4516D-CT0-10/05
Figure 1-1.
Block Diagram
MIX1IN2 41 42 MIX1IN1 40 Mixer1 MIX2IN MIX2O OSCGND MIX1O XCK VAF MIX2GND 39 38 37 Crystal Oscillator 36 35 34 Mixer2 33 IFIN1 32 IFIN2 31 IF Amp RSSI MUXDA D A Bias Bat low Detector DATRX + ETC 30 EXIN 29 Expander Ear Amp 27 28 RECO RECO2
GNDLO
f LO LO2 LO1 43 44 VCO3 :2 f LO f Ref3 Serial Bus :K
Demodulator
26
:N
RXO
fLO sin cos PCLO 1 1
(3)
Phase Comparator
25 + 1.5V Mic + 24 VRMIC 23 22
DAIN
MIC
MixerT +45 -45
:D2 :D1 :M12 :M12 (2) f Ref2 :2 Phase Comparator (1)
:D3 f Mod
MICO COIN CTC COUT
:10 :M :2 f Ref1 + Spl 1.5V Limiter Amp 13 14 15 16 17 18 Compressor
21 20
RFOGND RFO RFOVB
2 3 4 5 AGND 6 VBIAS VCO2 Loop Filter 7 VRF
VCO1 8 9 10
Phase Comparator 11 VDD 12
19
LIMIN
MLF LFGND MODIN
(1): PLL1: Modulator PLL
(2): PLL2: Mixer PLL
TXO OPOUT OPIN DACO (3): PLL3: Local oscillator (LO) PLL
VSS D C
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2. Pin Configuration
Figure 2-1. Pinning SSO44
PCLO RFOGND RFO RFOVB AGND VBIAS VRF MLF LFGND MODIN VDD VSS D C DACO OPOUT OPIN TXO LIMIN COUT CTC COIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
LO1 LO2 GNDLO MIX1IN2 MIX1IN1 MIX1O OSCGND XCK VAF MIX2O MIX2GND MIX2IN IFIN1 IFIN2 ETC EXIN RECO1 RECO2 RXO DAIN MIC MICO
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Table 2-1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Pin Description
Symbol PCLO RFOGND RFO RFOVB AGND VBIAS VRF MLF LFGND MODIN VDD VSS D C DACO OPOUT OPIN TXO LIMIN COUT CTC COIN MICO MIC DAIN RXO RECO2 RECO1 EXIN ETC IFIN2 IFIN1 MIX2IN MIX2GND MIX2O VAF XCK OSCGND MIX1O MIX1IN1 MIX1IN2 GNDLO LO2 LO1 Function Phase comparator local oscillator RF transmit output ground RF transmit output Power supply input of RF transmit output buffer Analog ground for RF part Decoupling capacitor of current reference Supply voltage for RF part Modulator loop filter Modulator loop filter ground Modulator input Supply voltage output for peripherals and internal supply of digital part Ground for LF analog and digital Data input of serial bus Clock input of serial bus D/A and data comparator output Operational amplifier output Operational amplifier input (inverting) Output of limiter amplifier Limiter input Compressor output Compressor time constant control analog output Compressor input Microphone amplifier output Inverting input of microphone amplifier Data comparator input Output of demodulator Symmetrical output of receive amplifier Expander input Expander time constant control analog output Symmetrical input of IF amplifier Input of Mixer2 IF amplifier and Mixer2 ground Mixer2 output Supply voltage for AF/IF parts Crystal oscillator input 11.15 MHz Oscillator ground Output of Mixer1 Symmetrical input of MIxer1 Ground of LO Tank elements for LO are connected to these pins
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3. System Description
Radio frequency IC for analog cordless telephone application in 26/50 MHz band (CTO standard). The IC performs full duplex communication. The transmitting and receiving frequency are depending on whether the IC is used in the handset or in the base station. Frequency converter comprise an FM transmitter with switchable output power and first receiver mixer in the same unit. A two-wire bus interface can be used for the frequency control as well as for switching the transmitter power amplifier and the receiver. Fine frequency adjust of reference quartz oscillator is programmable. The receive part is designed for a double conversion architecture. The incoming radio frequency signal will be filtered and amplified before reaching the first mixer. At this stage the RF signal will be converted down to the first intermediate frequency (10.7 MHz) by using a crystal oscillator (LO1). The transmit part contains two PLL controlled VCOs. The frequency modulation is accomplished by super-posing the incoming audio signal on the PLL control voltage. Final frequency is a product of mixing VCO1 with first local oscillator of receiver part (VCO3). The FM modulated carrier is amplified by externals power amplifier before entering the output filter and the antenna connector.
3.1
Adjustments for VCO1 and VCO2
To be able to use a wide frequency range for the VCOs (i.e., VCO2 26.3 MHz to 49.9 MHz) the two internal VCOs (VCO1 and VCO2, i.e., the VCOs of the transmit part) have a rough adjust and a fine adjust to increase the frequency range given by the phase comparator. The rough adjusts for these VCOs are correlated with the country setting. For every country there are two sets of VCO rough adjust settings, one for the base and one for the handset. See tables at channels frequencies and dividers. To compensate the variation in production there is a fine adjust for each of the VCOs. The fine adjusts of the internal VCOs could be set manually (for test purposes) or set by the automatic mode. Theoretically the sign of the changing (increase/ decrease when the voltage of the phase comparator is to high) is selectable, but we need value 1 () in all cases. Setting VCO1 (VCO2) under normal conditions: EAFA1 (EAFA2) = 1, automatic fine adjust VCO1(VCO2) enabled SAFA1 (SAFA2) = 1, sign of auto fine adjustment of VCO1 (VCO2) = 1.
3.2
Adjustment for VCO3
In order to increase the adjustment range of VCO3 with fixed external tank elements and/or for "band switching", especially for US frequencies, VCO3 has programmable capacitors inside. These capacitors can be added by serial bus (FA3 [4:0]) between LO1 and LO2. There are 31 steps available, every step adding a capacitor of 0.5 pF.
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3.3
Speed-up of the Loop Filter of PLL1 ("Modulator PLL")
To have a fast locking time for the modulator loop there is a precharge and a speed-up mode for the external loop filter. During receive mode (VCO3 enabled, VCO1 disabled) the modulator loop filter is precharged to about half of the internally regulated 2.5V charge-pump voltage. During the first 30 ms after enabling VCO1 the modulator phase comparator is in speed-up mode. In this mode the current of the pase comparator which charges the loop filter is much larger than in normal mode. Additionally to the automatically switched 30 ms speed-up mode, the speed-up can be activated for any time by setting the bit SU1.
3.4
Speed-up of the Loop Filter of PLL3 ("1st. LO.")
Similiar to PLL1, there is also a possibility to increase the locking speed of PLL3. This can be done by setting the bit SU3. Having done this, the charge pump at the output of the phase comparator has a bigger current capability and therefore charges the external capacitors faster.
3.5
Adjustment of the Modulator Gain
To fulfil the different requirements of the different countries three conversion gains of the modulator are selectable by the bits GMOD [1:0] (R6: D2, D3). Country settings see tables at channel frequencies and dividers. Ranges see electrical characteristics at RF transmitter.
3.6
Modulator PLL
The fractional divider has been chosen to increase the reference frequency of the modulator PLL. Q1 557.5 kHz = f Mod / P 1 + --------- 223 P1: integer part of the fractional divider (M = 1) Q1: fractional part of the fractional divider (M = 1) f Mod Q 1 = 223 x -------------------------- - P 1 557.5 kHz 223 = 557.5 kHz -------------------------2.5 kHz The frequency step 2.5 kHz is a fraction of the reference frequency 557.5 kHz. In fact, the fractional divider divides Q1 times by (P1 + 1) and (223 - Q1) times by P1 during 223 cycles. Q 1 x ( P 1 + 1 ) + ( 223 - Q 1 )P 1 Q1 ----------------------------------------------------------------------------- = P 1 + --------223 223 For each comparison cycle (fRef1 = 557.5 kHz), the accumulator content is incremented by the Q1 value and the divider divides by the P1 value. When the accumulator value reaches or exceeds 223, the divider divides by the value (P1 + 1). Then, the accumulator holds the excess value (accumulator value - 223). After 223 cycles, the correct division is executed.
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3.7 Serial Bus Interface
The circuit is remoted by an external microcontroller through the serial bus. The data is a 12-bit word: A0 - A3: address of the destination register (0 to 15) D7 - D0: contents of register The data line must be stable when the clock is high and data must be serially shifted. After 12 clock periods, the transfer to the destination register is (internally) generated by a low to high transition of the data line when the clock is high. Figure 3-1. Serial Bus
Data Microprocessor Clock
D C
Figure 3-2.
Serial Bus Transmission
Data (D)
D0
D1
D2
A0
A1
A2
A3
Clock (C) 1st word 2nd word Transfer condition
Word transmission
Figure 3-3.
Serial Bus Structure
Data 4 Clock 8
0 Address Decoder 128 Latches
15
Commands
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Figure 3-4.
Serial Bus Timing Diagram
Data (D) A1 A2 A3 D0
Clock (C)
tsud
thd
tch
tcl
teon
teh
teoff
3.8
Content of Internal Registers
The registers have the following structure
D7 D6 D5 D4 D3 D2 D1 D0
R0: Reference for D/A converter
MUXDA DA6 DA5 DA4 DA3 DA2 DA1 DA0
MUXDA: DA(0:6):
D/A multiplexing VBAT/RSSI Reference voltage D/A
R1: Gain of earpeace amplifier and demodulator
GEA4 GEA3 GEA2 GEA1 GEA0 GDEM free free
GEA[0:4]: GDEM:
Gain of earpeace amplifier; "0" is LSB, "4" is MSB Demodulator gain (1 = low gain)
R2: Switches and mutes for receive and data reception
DATRX BEXP EEA ERXO ERX1 ERXHF MRX ERX2
DATRX: BEXP: EEA: ERXO: ERX1: ERXHF: MRX: ERX2:
Switch data comparator output to "DACO"-pin Bypass expander Enable earpiece amplifier Enable RXO output driver Enable RX low frequency part 1 Enable Mixer2 and IF-amplifier Mute RX low frequency path (expander) keeping circuit enabled Enable RX low frequency part 2 (expander)
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R3: Switches and mutes for transmit and power managemant
PDVDD RBAT free free free free MTX ETX
PDVDD: RBAT: MTX: ETX:
Enable pull-down transistor in power-down mode Battery detection high/low range Mute TX low frequency path (compressor) keeping circuit enabled Enable TX low frequency part
R4: free (not used, for future extensions )
free free free free free free free free
R5: Gain VCO2
free free KV23 KV22 KV21 M12 free free
KV2[1:3]: M12:
Gain of VCO2 Double phase comparator frequency of PLL2
R6: Miscellaneus settings in synthesizer part
ETXO M1CP FRMT IMIXI GMOD1 GMOD0 SU1 (TM)
Enable HF-transmit output Changes 1 dB compression point and current consumption of Mixer1 ("0" -> high, "1" -> low) FRMT: Output frequency range of MixerT IMIXI: Invert inputs of phase comparator in PLL2 GMOD[0:1]: Modulation gain of VCO1 SU1: Speed-up phase comparator for PLL1 (TM): Enable the internal test mode. It is mandatory that TM is kept to "0"! (if not 0, the circuit will not work as expected or described here in this paper) R7: PLL1 setting
DR1I1 DR1I0 RA11 RA10 DV1I3 DV1I2 DV1I1 DV1I0
ETXO: M1CP:
DR1I[0:1]: Additional divider reference frequency PLL1 RA1[0:1]: Rough adjustment VCO1 DV1I[0:3]: Divider setting PLL1 integer part; "0" is LSB, "3" is MSB R8: Divider PLL1 fractional part
DV1F7 DV1F6 DV1F5 DV1F4 DV1F3 DV1F2 DV1F1 DV1F0
DV1F[0:7]: Divider setting PLL1 fractional part; "0" is LSB, "7" is MSB
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R9: Divider PLL3 LSBs
DV3I7 DV3I6 DV3I5 DV3I4 DV3I3 DV3I2 DV3I1 DV3I0
R10: Divider PLL3 MSBs and MSB of VCO3 fine adjustment
FA34 DV3I14 DV3I13 DV3I12 DV3I11 DV3I10 DV3I9 DV3I8
FA34: Fine adjustment VCO3 (frequency reduction) MSB DV1I[0:14]: Divider setting PLL3 integer part; "0" is LSB, "14" is MSB R11: Setting PLL2 and VCO3
FA33 FA32 FA31 FA30 AMIX2 AMIX1 RA21 RA20
FA3[0:4]: Fine adjustment of VCO3 (frequency reduction); "0" is LSB, "4" is MSB AMIX[1:2]: Lengthening antibacklash signal PLL2 RA2[1:0]: Rough adjustment VCO2 R12: Divider for country setting, fine adjustment oscillator
FAOS2 FAOS1 FAOS0 D31 D30 D20 D11 D10
FAOS[0:2]: Fine adjustment of crystal oscillator (frequency reduction); "0" is LSB, "2" is MSB D3[0:1]: Setting divider D3 D20: Setting divider D2 D1[0:1]: Setting divider D1 R13: VCO1 enable and fine adjustment
EVCO1 SAFA1 EAFA1 FA14 FA13 FA12 FA11 FA10
EVCO1: SAFA1: EAFA1: FA1(0:4):
Enable VCO1 Sign for automatic fine adjustment of VCO1 Enable automatic fine adjustment of VCO1 Manual fine adjustment of VCO1 (frequency reduction); "0" is LSB, "4" is MSB
R14: VCO2 enable and fine adjustment
EVCO2 SAFA2 EAFA2 FA24 FA23 FA22 FA21 FA20
EVCO2: SAFA2: EAFA2: FA2(0:4):
Enable VCO2 and MixerT Sign for automatic fine adjustment of VCO2 Enable automatic fine adjustment of VCO2 Manual fine adjustment of VCO2 (frtequency reduction); "0" is LSB, "4" is MSB
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R15: VCO3 enable, speed-up and referencq frequency, crystal oscillator enable
EVCO3 EOSC SU3 E25K E12K5 E10K E6K25 E5K
EVCO3: Enable VCO3 and Mixer1 EOSC: Enable crystal oscillator (11.15 MHz) SU3: Speed-up phase comparator for PLL3 E25K: Selection phase comparator frequency for PLL3: fRef3 = 25 kHz E12K5: Selection phase comparator frequency for PLL3: fRef3 = 12.5 kHz E10K: Selection phase comparator frequency for PLL3: fRef3 = 10 kHz E6K25: Selection phase comparator frequency for PLL3: fRef3 = 6.25 kHz E5K: Selection phase comparator frequency for PLL3: fRef3 = 5 kHz E5K, E6K25, E10K, E15K5, E25K = 0: Selection phase comparator frequency for PLL3: fRef3 = 2.5 kHz
4. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Junction temperature Ambient temperature Storage temperature Power dissipation Tamb = 60C Symbol VBatt, VDD Tj Tamb Tstg Ptot Value 5.5 +125 -25 to +75 -50 to +125 0.9 Unit V C C C W
5. Thermal Resistance
Parameters Junction ambient SSO44 Symbol RthJA Value 70 Unit K/W
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6. Electrical Characteristics
Tamb = +25C, VRF = VAF = RFOVB = 3.6V, all bits set to "0", unless otherwise specified. Test circuit, see Figure 8-1 on page 18. Crystal specifications, see table "Crystal Specifications". Parameters Power Supply Operating voltage range Current Consumption Operating current in inactive mode (low voltage) Operating current in standby mode Operating current in RX mode "waiting for RSSI" Operating current in RX mode "receiving data" Operating current in conversation mode: all blocks enabled Charge Pump of LL1 Charge pump output voltage Precharge voltage at the loop filter Charge pump output current in speed-up mode Charge pump output current Charge pump leakage current Charge Pump of PLL3 Charge pump output voltage Charge pump output current in speed-up mode Charge pump output current Charge pump leakage current Input frequency range Output frequency Input resistance Input capacitance Output impedance Voltage gain Input noise voltage MIX1IN1/MIX1IN2 to GND MIX1IN1/MIX1IN2 to GND MIX1O MIX1IN1/2 -> MIX1O "Loaded" (330 with serial capacitance) "Unloaded" 210 Output high VPCLO = 1.25V, output low VPCLO = 1.25V, output high VPCLO = 1.25V, output low VPCLO = 1.25V, output high VPCLO = 1.25V, output tristate 2.38 220 -420 80 -160 -50 20 10.7 3.0 3.5 330 11.5 17.5 9 390 2.5 2.63 420 -220 160 -80 +50 50 V A A A A nA MHz MHz k pF dB dB nV Hz-1/2 Output high SB127 = 1, SB119 = 0 VMLF = 1.25V, output low VMLF = 1.25V, output high VMLF = 1.25V, output low VMLF = 1.25V, output high VMLF = 1.25V, output tristate 2.38 1.15 190 -400 4.3 -8 -150 6.2 -6.2 2.5 1.4 2.63 1.65 400 -190 8 -4.3 +150 V V A A A A nA VRF = VAF = RFOVB = 2.9V VDD = 0V VRF = VAF = RFOVB = 3.6V ERXHF = EVCO3 = EOSC = 1 ERXHF = EVCO3 = EOSC = ERX1 = ERXO = 1 ERXHF = EVCO3 = EOSC = ERX1 = ERXO = ERX2 = EEA = EVCO2 = ETXO = 1 no load at RFO pin 3 30 30 65 100 7.5 8.5 85 350 10.4 11.5 A A mA mA 3.1 3.6 5.2 V Test Conditions Symbol Min. Typ. Max. Unit
20
29
mA
Receiver Input Mixer (Mixer1), EVCO3 = EOSC = 1
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6. Electrical Characteristics (Continued)
Tamb = +25C, VRF = VAF = RFOVB = 3.6V, all bits set to "0", unless otherwise specified. Test circuit, see Figure 8-1 on page 18. Crystal specifications, see table "Crystal Specifications". Parameters Test Conditions "Loaded" (330 with serial capacitance) M1CP=0 M1CP=1 "unloaded" M1CP=1 "Loaded" (330 with seial capacitance) M1CP=0 MIX2IN to GND MIX2IN to GND MIX2O MIX2IN -> MIX2O "Loaded" (1500 with serial capacitance) "Loaded" (1500 with serial capacitance) "Loaded" (1500 with serial capcitance) 2.0 2.5 1200 13 32 80 Symbol Min. Typ. 140 40 100 430 3.0 3 1500 15 4.0 3.5 1800 17 Max. Unit mV mV mV mV k pF dB mV mV
Input 1-dB compression point
Third order input intercept point Input resistance Input capacitance Output impedance Voltage gain Input 1-dB compression point Third order input intercept point Recovered audio at RXO, demodulator gain AM rejection ratio Gain reference level = G.R.L. (gain = 0 dB) Gain versus input signal level ("gain tracking")
IF Mixer (Mixer2), EOSC = ERXHF = 1; Input Frequency: 10.7 MHz
IF Amplifier and Demodulator, ERXHF=1, ERX1=1, ERXO=1; Input Signal: 450 kHz, 500 V, FM-modulation Frequency = 1 kHz GDEM=0 GDEM=1 30% AM, 2.5 kHz FM 180 90 35 mV/kHz mV/kHz dB
Expander, ERX2 = 1; 470 nF from ETC to GND (VSS) 70 VEXIN = 10 dB less than G.R.L. VEXIN = 20 dB less than G.R.L. VEXIN = 30 dB less than G.R.L. VEXIN = step 25 mV -> 50 mV measure time after step, when output voltage has 0.75 times of final value VEXIN = step 50 mV -> 25 mV measure time after step, when output voltage has 1.5 times of final value 9.5 GEA[4:0]=0 GEA[4:0]=16 GEA[4:0]=31 Maximum gain; 1 k load; increase input voltage until distortion 5% 0 16 31 0.8 4.8 7.3 1 17 32 1 5 12.5 -11 -21 -35 80 -10 -20 -30 16 90 -9 -19 -25 mVrms dB dB dB ms
Attack time
Release time Input resistance Minimum gain Medium gain Maximum gain Gain adjust step Output voltage swing Input resistance
16 15 2 18 33 1.2
ms k dB dB dB dB Vpp k
Earpiece Amplifier, EEA = 1, ERX2 = 1, BEXP = 1; Apply Input Voltage to EXIN; Measure Differentially at RECO1/2
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6. Electrical Characteristics (Continued)
Tamb = +25C, VRF = VAF = RFOVB = 3.6V, all bits set to "0", unless otherwise specified. Test circuit, see Figure 8-1 on page 18. Crystal specifications, see table "Crystal Specifications". Parameters IF Amplifier: RSSI Input frequency Input resistance VIF = 0 V starting from 0 increase RSSI-level until mean of sampled signal at DACO is 0.5. RSSI-level = ION0 RSSI sensitivity VIF = 25.4 V, f = 450 kHz increase RSSI level again until mean of sampled signal at DACO is 0.5. RSSI-level = ION1 RSSI-sensitivity = ION1-ION0 1 ERXHF=1 1.6 450 2.0 2.5 kHz k Test Conditions Symbol Min. Typ. Max. Unit
RSSI input voltage dynamic range RSSI level number of programmable steps (see folowing table "RSSI Level Programming (Typical Values) RSSI level step size in the logarithmic region 0.35
65
dB
127
dB
0.46
0.6
dB
Table 6-1.
RSSI Level Programming (Typical Values)
Input Voltage VIF (V) 0 25.4 42.4 424 4240 42400 RSSI Level (Decimal) 5 8 14 54 97 111
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7. Electrical Characteristics
Tamb = +25C, VRF = VAF = RFOVB = 3.6V, all bits set to "0", unless otherwise specified. Test circuit, see Figure 8-1 on page 18. Parameters Hysteresis Threshold voltage Input impedance Output high voltage Output low voltage Output impedance Battery Switch "Off" threshold Decrease VBAT until internal switch between VBAT and VDD becomes high ohmic ("off") Increase VBAT until internal switch between VBAT and VDD becomes low ohmic ("on") Difference between on and off threshold 2.85 2.95 3.1 V DAIN DACO, without load (CMOS-output -> full swing) DACO, without load (CMOS-output -> full swing) DACO Test Conditions Symbol Min. Typ. 50 1.5 100 3.5 0.1 6 Max. Unit mV V k V V k Data Comparator, ERX1 = DATRX = 1
"On" threshold Hysteresis "Off"-leakage current Switch "On"-resistance
3.1
3.2 250
3.35
V mV
10 50 DA[6:0] = 127, RBAT = 1 DA[6:0] = 27, RBAT = 1 DA[6:0] = 127, RBAT = 0 DA[6:0] = 0, RBAT = 0 3.7 3.05 4.75 3.83 3.5 852.5 3.95 3.2 5.05 4.1 7.5 952.5 80 3 0.8 2 4.1 3.35 5.25 4.27 11.5 1052.5
A V V V V mV mV dB MHz Vrmsp
Battery Management, MUXDA = 1 Maximum bat low Minimum bat low over switch Maximum bat high Minimum bat high Adjust step Maximum - Minimum Microphone Amplifier, ETX=1 Open loop gain Gain bandwidth product Input noise voltage, BW = 300 Hz to 3.4 kHz, psophometrically weighted Compressor, ETX = 1; 470 nF from CTC to GND (VSS) Gain reference level = G.R.L. (gain = 0 dB) Gain versus input signal level ("gain tracking") VCOIN = 20 dB less than G.R.L. VCOIN = 40 dB less than G.R.L. VCOIN = 50 dB less than G.R.L. VCOIN = 60 dB less than G.R.L VCOIN = step 31.6 mV -> 126 mV, (-30 dBV -> -18 dBV) measure time after step, when output voltage has 1.5 times of final value 298 9 19 22 316 10 20 25 30 340 11 21 28 mVrms
dB
Attack time
3.5
ms
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7. Electrical Characteristics (Continued)
Tamb = +25C, VRF = VAF = RFOVB = 3.6V, all bits set to "0", unless otherwise specified. Test circuit, see Figure 8-1 on page 18. Parameters Test Conditions VCOIN = step 126 mV -> 31.6 mV (-18 dBV -> -30 dBV) measure time after step, when output voltage has 0.75 times of final value 14 Symbol Min. Typ. Max. Unit
Release time
14.4
ms
Input resistance Splatter Amplifier, ETX = 1 Open loop gain Gain bandwidth product Maximum output voltage swing Limiter Amplifier, ETX = 1, Tj = 25C Gain for signals below limitation Distortion for signals below limitation Maximum output voltage swing (above limitation, clipping) LIMIN -> TXO, 20 mVRMS applied to LIMIN (AC coupled) LIMIN -> TXO, 20 mVRMS applied to LIMIN (AC coupled)
19.5 90 150
26
k dB kHz Vpp
2.4
26 2
dB %
1.8
2.1
2.35
Vpp
Input resistance at LIMIN 15 20 25 k Note: The gain and maximum output voltage swing of the limiter amplifier changes with temperature to compensate the temperature dependancy of MODIN ("tx conversion gain" of RF transmit part), fundamentally determined by the structure of the circuitry. RF Transmitter, ETXO = EVCO1 = EVCO2 = EVCO3 = EOSC = 1; Tj = 25C MODIN input impedance RFO output impedance RFO output voltage level Highest operating frequency Load = 200 o ETXO = 0; no load USA Base Channel 9 (US1b9) For the complete programming see "Channel Frequencies, Dividers and Country Settings" on page 20" USA1: GMOD[1:0] = 00; fMod = ~7.6 MHz TX conversion gain MODIN - RFO USA2: GMOD[1:0] = 01; fMod = ~5.7 MHz France: GMOD[1:0] = 01; fMod = 4.3 MHz GMOD[1:0] = 00; fMod = 4.3 MHz Spain/Netherlands: GMOD[1:0] = 10; fMod = 1.8 MHz Demodulated distortion THD MODIN - RFO Modulation frequency: 1 kHz US: F = 4.0 kHz France: F = 2.5 kHz 49.99 00 70 230 100 300 130 390 0.3 k V MHz
5.2
kHz/V
5.2
kHz/V
3.8 2.7
kHz/V kHz/V
7.9 1.5 5
kHz/V %
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7. Electrical Characteristics (Continued)
Tamb = +25C, VRF = VAF = RFOVB = 3.6V, all bits set to "0", unless otherwise specified. Test circuit, see Figure 8-1 on page 18. Parameters Test Conditions Symbol Min. Typ. Max. Unit Note: The tx conversion gain of the RF transmitter is somehow dependent on temperature. This is determined by the fundamental principle of this circuitry. Means have been taken inside the limiter amplifier, being in the signal path before MODIN, which are able to completely compensate this temperature behavior. Logical Part Inputs: C, D Low voltage input High voltage input Input leakage current (0 < VI < VDD) Input leakage current Pin XCK (0 < VI < VDD) Serial bus (Figure 8-2) Data set-up time Data hold time Clock low time Clock high time Hold time before transfer condition Data low pulse on transfer condition Data high pulse on transfer condition tsud thd tcl tch teon teh teoff 0.2 x VDD
Vil Vih Ii
0.8 x VD
D
-1 -5
+5 +5
A A
0.1 0 2 2 0.1 0.2 0.2
s s s s s s s
8. Fine Adjustment of the Oscillator Frequency
To set the frequency of the oscillator exact to 11.15 MHz, the frequency is adjustable in 8 steps, by adding 3 different internal capacities the frequency could be reduced. Parameters Oscillator frequency without reduction Test Conditions/Pins FAOS (0:2) = 0 FAOS2 FAOS1 FAOS0 0 0 1 0 1 0 1 0 0 1 0 1 Min. Typ. 11.15 + 140 280 560 700 Max. Unit MHz
Changing of oscillator frequency with FOSC reduction
Hz
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Figure 8-1.
Test Circuit
BZT55C51
RFO
56K 10N
68N
MIX1IN2
24K
10N
10N
MIX1IN1
RFOVB
470N
5P
44
MIX1O 330
10N
1 0
1
PCLO RFOGND
LO1 LO2 GNDLO MIX1IN2 MIX1IN1
TX-/Modulator470N
RFO RFOVB
10N VRF
MODIN
VBIAS VRF MLF LFGND MODIN
MIX1O OSCGND
1 2
5.6K 1U 100N
XCK VAF MIX2O MIX2GND MIX2IN IFIN1 IFIN2 ETC EIN RECO1 RECO2 RXO DAIN MIC MICO
23
VAF
470N MIX2O
MPU serial interface
DATA 470N
VDD VSS DATA CLOCK DACO
11.15M
Loop Filter
AGND
1500 470N MIX2IN 10N
CLOCK
OPOUT OPIN
10K
TXO LIMIN COUT CTC
22
DACO
CIN
10N
IFIN1
470N
10K
10N
IFIN2
850
44K
220N
EIN
85
RECO1
4.7N 1000
22UF
RECO2
RXO
47N
220N
47N
DAIN
SPLAIN
COUT
OPOUT
COUT
LIMIN
VDD
MICO
NOTE:
This schematics is only a basic(simplified) representation of the current production test circuit
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MICIN
CIN
10N
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Figure 8-2.
Duplex Filter
Antenna
4516D-CT0-10/05
+VB
47p CFW 450 E 47p 11.15 MHz 100n 390 5.6k 100n 470n SFE 10.7 MS 2
100n
100n
Application Circuit
RX
RXGND
41 39 28 Expander Ear Amp 27 Mixer1 Crystal Oscillator RSSI Mixer2 IF - Amp 36 35 33 31 29 32 42 40 38 37 30 34
68n
10n
220n
24K D A Demodulator + 43 5.6p 44
fLO fLO :N Phase
Comparator DATRX fRef3 Serial Bus
MUXDA
26
1K 22n 20K
7.5K 100n 8.2K 25 0.75n 22n 15n
56K
2x BZT55C51
VCO3 :2 fLO sin cos
:K
Bias Bat low Detector
Hand : 100nH Base : 230nH 1 1
(3)
+
1.5V
TXGND
MixerT
+45 -45
Mic :D2 :D1 :M12 :M12 fRef2 :2 : (PM + QM ) 223 fMod :M
24
2.2K
470n
+
22K VRMIC 23
Electret Microphone
:10 Compressor 22 21 :2 470n 220n
TX (2)
100n 2 3 Comparator 1n 330
+VB
(1)
:D3
10
100n
Phase
1uH
fRef1
VCO1 9 10
20
2.2K
+
Phase
Comparator 11 12 13 14 Spl Amp 1.5V
4.7K
VCO2
5 6 7 8
Loop Filter
4
-
Limiter
19
2.2n
12K 56n 15 16 17 18 100K
20
+VB
5.6K 1n 1u 100n 10K 15K
15n 10K 12K
TX DATA
12n
(1): PLL1: Modulator PLL
4.7n
(2): PLL2: Mixer PLL (3): PLL3: Local oscillator (LO) PLL
DACO C D VDD
C
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19
9. Channel Frequencies, Dividers and Country Settings
To meet all requirements of various countries - France (F), Spain (E), Netherlands (NL), USA, Portugal (P), Taiwan, New Zealand and Korea - and modes - base (b), handset (h) - several bits have to be set which do not change for the different channels. These settings are called country settings. * The country-setting bits contain: * Rough adjustments for 2 VCOs * Setting three integer divider in the mixer PLL and modulator PLL * Conversion gain adjustment of mixer PLL * Modulator gain * Setting of the pulling direction of PLL2 (value dependent, if TX frequency is higher or lower than LO frequency) * Demodulator gain
Name Register RA1[1:0] RA2[1:0] D1[1:0] D20 M12 D3[1:0] KV[3:1] GMOD[1:0] IMIXI
Function Rough adjust VCO1 Rough adjust VCO2 Integer divider D1 Integer divider D2 Integer divider M12 Integer divider D3 Conversion gain VCO2 Modulator gain Reverse inputs of PC of PLL Additional divider M for reference frequency fRef1 Frequency range Mixer T Demodulator gain
Notes 00: is the highest frequency 00: is the highest frequency Division by 2, 4, 6, 8 Division by 6, 8 Doubles reference frequency of PLL2 when set to "1" Division by 1, 2, 4 00: gain minimal 0: if fVCO2 lower than fVCO3 "0" means no reduction, >0 only necessary in E, NL, Portugal 0: output frequency < 5 MHz 0: high gain 1: low gain
Number of Positions 3 4 4 2 2 3 6 3 2
DR1[1:0]
4
FRMT GDEM Note:
2 2
Setting the fractional dividers: For N, QM, send the binary equivalent of the numbers given below. For PM (integer part of modulator PLL), send the D2 complement (16 - PM) i.e., Fb1 (PM = 7, QM = 159 => integer: send 16 - PM = 9, fractional: send 159)
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10. Tables for Programming of the Dividers (Refer to Block Diagram)
Table 10-1.
D11 (bit) 0 0 1 1
Divider D1 for PLL2
D10 (bit) 0 1 0 1 Decimally 0 1 2 3 D1 (Block Diagram),if M12 = 0 2 8 6 4 D1 (Block Diagram),if M12 = 1 1 4 3 2
Table 10-2.
D20 (bit) 0 0
Divider D2 between PLL1 and PLL2
Decimally 0 1 D2 (Block Diagram),if M12 = 0 6 8 D2 (Block Diagram),if M12 = 1 3 4
Table 10-3.
D31 (bit) 0 0 1 1
Divider D3 for PLL1
D30 (bit) 0 1 0 1 Decimally 0 1 2 3 D3 (Block Diagram) 1 2 6 4
10.1
Divider M for Reference Frequency of PLL1
There are several countries like Spain, the Netherlands and Portugal with relatively low modulator frequencies fMod. In case of modulation there will be a big maximum time shift between pulses coming from fractional divider and pulses coming from reference frequency divider. As a consequence the phase comparator enters an undesired operation mode. To avoid entering this operation mode the reference frequency fRef1 has to be reduced by a factor M. Simultaneously, keeping fMod constant, the factors of fractional dividers have to be changed as well. The connection between the additional reference frequency divider M and the factors PM and QM of fractional divider is given below. The subscript M denotes which value of M refers to the factors PM and QM of fractional divider. The formulas take into account that the numerator of the fraction QM/223 must not exceed 223. PM = P1 x M + integer (Q x M/223) QM = Q1 x M - 223 x integer (Q1 x M/223)
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10.2
France Base
Country Setting
RA2[1:0] 11 min D1[1:0] 11 D1 = 4 D20 1 D2 = 8 D3[1:0] 01 D3 = 2 KV2[3:1] 100 GMOD[1:0] 01 (1) IMIXI 0 supra DR1I[1:0] 00 M=1 FRMT 0 low GDEM 0 high gain 00 max
Table 10-4.
Name Setting Value Note:
RA1[1:0]
Alternatively, GMOD[1:0] could be set to "00". This reduces the TX conversion gain (MODIN -> RFO) from about 3.8 kHz/V to about 2.7 kHz/V, a value, which should be still sufficient for a maximum f of kHz 2.5 that is useful in the French case.
Table 10-5.
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
TX Channel (MHz) 26.3125 26.3250 26.3375 26.3500 26.3625 26.3750 26.3875 26.400 26.4125 26.4250 26.4375 26.4500 26.4625 26.4750 26.4875 Rx Channel Frequency (MHz) 41.3125 41.3250 41.3375 41.3500 41.3625 41.3750 41.3875 41.4000 41.4125 41.4250 41.4375 41.4500 41.4625 41.4750 41.4875 fLO = 1/2 fVCO3 (MHz) 30.6125 30.6250 30.6375 30.6500 30.6625 30.6750 30.6875 30.7000 30.7125 30.7250 30.7375 30.7500 30.7625 30.7750 30.7875 DV3I[14:0] = N 4898 4900 4902 4904 4906 4908 4910 4912 4914 4916 4918 4920 4922 4924 4926
10.2.1 France Modulation Loop Frequency and Divider fMod = 4.3 MHz, PM = 7, QM = 159, M = 1
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10.3 France Hand
Country Setting
RA2[1:0] 01 D1[1:0] 11 D1 = 4 D20 1 D2 = 8 D3[1:0] 01 D3 = 2 KV2[3:1] 101 GMOD[1:0] 01 (1) IMIXI 1 infra DR1I[1:0] 00 M=1 FRMT 0 low GDEM 0 high gain 00 max
Table 10-6.
Name Setting Value Note:
RA1[1:0]
Alternatively, GMOD[1:0] could be set to "00". This reduces the TX conversion gain (MODIN -> RFO) from about 3.8 kHz/V to about 2.7 kHz/V, a value, which should be still sufficient for a maximum f of kHz 2.5 that is useful in the French case.
Table 10-7.
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
TX Channel Frequency (MHz) 41.3125 41.3250 41.3375 41.3500 41.3625 41.3750 41.3875 41.4000 41.4125 41.4250 41.4375 41.4500 41.4625 41.4750 41.4875 RX Channel Frequency (MHz) 26.3125 26.3250 26.3375 26.3500 26.3625 26.3750 26.3875 26.4000 26.4125 26.4250 26.4375 26.4500 26.4625 26.4750 26.4875 fLO = 1/2 fVCO3 (MHz) 37.0125 37.0250 37.0375 37.0500 37.0625 37.0750 37.0875 37.1000 37.1125 37.1250 37.1375 37.1500 37.1625 37.1750 37.1875 DV3I[14:0] = N 5922 5924 5926 5928 5930 5932 5934 5936 5938 5940 5942 5944 5946 5948 5950
10.3.1 France Modulation Loop Frequency and Divider fMod = 4.3 MHz, PM = 7, QM = 159, M = 1
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10.4
Spain Base
Country Setting
RA2[1:0] 10 D1[1:0] 00 D1 = 2 D20 1 D2 = 8 D3[1:0] 11 D3 = 4 KV2[3:1] 001 GMOD[1:0] 10 IMIXI 1 infra DR1I[1:0] 11 M=4 FRMT 1 high GDEM 1 low gain 10
Table 10-8.
Name Setting Value
RA1[1:0]
Table 10-9.
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12
Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
TX Channel Frequency (MHz) 31.025 31.050 31.075 31.100 31.125 31.150 31.175 31.200 31.250 31.275 31.300 31.325 RX Channel Frequency (MHz) 39.925 39.950 39.975 40.000 40.025 40.050 40.075 40.100 40.150 40.175 40.200 40.225 fLO = 1/2 fVCO3 (MHz) 29.225 29.250 29.275 29.300 29.325 29.350 29.375 29.400 29.450 29.475 29.500 29.525 DV3I[14:0] = N 4676 4680 4684 4688 4692 4696 4700 4704 4712 4716 4720 4724
10.4.1 Spain Modulation Loop Frequency and Divider fRef1 = 557.5 kHz/4, fMod = 1.8 MHz/4,PM = 12,QM = 204, M = 4
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10.5 Spain Hand
Table 10-10. Country Setting
Name Setting Value RA1[1:0] 10 RA2[1:0] 01 high D1[1:0] 00 D1 = 2 D20 1 D2 = 8 D3[1:0] 11 D3 = 4 KV2[3:1] 100 GMOD[1:0] 10 high IMIXI 0 supra DR1I[1:0] 11 M=4 FRMT 1 high GDEM 1 low gain
Table 10-11. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 TX Channel Frequency (MHz) 39.925 39.950 39.975 40.000 40.025 40.050 40.075 40.100 40.150 40.175 40.200 40.225 RX Channel Frequency (MHz) 31.025 31.050 31.075 31.100 31.125 31.150 31.175 31.200 31.250 31.275 31.300 31.325 fLO = 1/2 fVCO3 (MHz) 41.725 41.750 41.775 41.800 41.825 41.850 41.875 41.900 41.950 41.975 42.000 42.025 DV3I[14:0] = N 6676 6680 6684 6688 6692 6696 6700 6704 6712 6716 6720 6724
10.5.1 Spain Modulation Loop Frequency and Divider fRef1 = 557.5 kHz/4, fMod = 1.8 MHz/4,PM = 12,QM = 204, M = 4
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10.6
Netherlands Base
Table 10-12. Country Setting
Name Setting Value RA1[1:0] 10 RA2[1:0] 10 low D1[1:0] 00 D1 = 2 D20 1 D2 = 8 D3[1:0] 11 D3 = 4 KV2[3:1] 001 GMOD[1:0] 10 high IMIXI 1 infra DR1I[1:0] 11 M=4 FRMT 1 high GDEM 1 low gain
Table 10-13. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 TX Channel Frequency (MHz) 31.0375 31.0625 31.0875 31.1125 31.1375 31.1625 31.1875 31.2125 31.2375 31.2625 31.2875 31.3125 RX Channel Frequency (MHz) 39.9375 39.9625 39.9875 40.0125 40.0375 40.0625 40.0875 40.1125 40.1375 40.1625 40.1875 40.2125 fLO = 1/2 fVCO3 (MHz) 29.2375 29.2625 29.2875 29.3125 29.3375 29.3625 29.3875 29.4125 29.4375 29.4625 29.4875 29.5125 DV3I[14:0] = N 4678 4682 4686 4690 4694 4698 4702 4706 4710 4714 4718 4722
10.6.1 Netherlands Modulation Loop Frequency and Divider fRef1 = 557.5 kHz/4, fMod = 1.8 MHz/4,PM = 12,QM = 204, M = 4
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10.7 Netherlands Hand
Table 10-14. Country Setting
Name Setting Value RA1[1:0] 10 RA2[1:0] 01 high D1[1:0] 00 D1 = 2 D20 1 D2 = 8 D3[1:0] 11 D3 = 4 KV2[3:1] 001 GMOD[1:0] 10 high IMIXI 0 supra DR1I[1:0] 11 M=4 FRMT 1 high GDEM 1 low gain
Table 10-15. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 TX Channel Frequency (MHz) 39.9375 39.9625 39.9875 40.0125 40.0375 40.0625 40.0875 40.1125 40.1375 40.1625 40.1875 40.2125 RX Channel Frequency (MHz) 31.0375 31.0625 31.0875 31.1125 31.1375 31.1625 31.1875 31.2125 31.2375 31.2625 31.2875 31.3125 fLO = 1/2 fVCO3 (MHz) 41.7375 41.7625 41.7875 41.8125 41.8375 41.8625 41.8875 41.9125 41.9375 41.9625 41.9875 42.0125 DV3I[14:0] = N 6678 6682 6686 6690 6694 6698 6702 6706 6710 6714 6718 6722
10.7.1 Netherlands Modulation Loop Frequency and Divider fRef1 = 557.5 kHz/4, fMod = 1.8 MHz/4,PM = 12,QM = 204, M = 4
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10.8
U.K. Base
Table 10-16. Country Setting
Name Setting Value RA1[1:0] 10 RA2[1:0] 10 low D1[1:0] 00 D1 = 2 D20 1 D2 = 8 D3[1:0] 11 D3 = 4 KV2[3:1] 001 GMOD[1:0] 10 high IMIXI 1 infra DR1I[1:0] 11 M=4 FRMT 1 high GDEM 1 low gain
Table 10-17. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 TX Channel Frequency (MHz) 31.0375 31.0625 31.0875 31.1125 RX Channel Frequency (MHz) 39.9375 39.9625 39.9875 40.0125 fLO = 1/2 fVCO3 (MHz) 29.2375 29.2625 29.2875 29.3125 DV3I[14:0] = N 4678 4682 4686 4690
10.8.1 U.K. Modulation Loop Frequency and Divider fRef1 = 557.5 kHz/4, fMod = 1.8 MHz/4,PM = 12,QM = 204, M = 4
10.9
U.K. Handset
Table 10-18. Country Setting
Name Setting Value RA1[1:0] 10 RA2[1:0] 01 high D1[1:0] 00 D1 = 2 D20 1 D2 = 8 D3[1:0] 11 D3 = 4 KV2[3:1] 001 GMOD[1:0] 10 high IMIXI 0 supra DR1I[1:0] 11 M=4 FRMT 1 high GDEM 1 low gain
Table 10-19. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 TX Channel Frequency (MHz) 39.9375 39.9625 39.9875 40.0125 RX Channel Frequency (MHz) 31.0375 31.0625 31.0875 31.1125 fLO = 1/2 fVCO3 (MHz) 41.7375 41.7625 41.7875 41.8125 DV3I[14:0] = N 6678 6682 6686 6690
10.9.1 U.K. Modulation Loop Frequency and Divider fRef1 = 557.5 kHz/4, fMod = 1.8 MHz/4,PM = 12,QM = 204, M = 4
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10.10 USA Base
Table 10-20. Country Setting Channels (Channel 1 - 10, USA1)
Name Setting Value RA1[1:0] 10 RA2[1:0] 00 max D1[1:0] 01 D1 = 8 D20 1 D2 = 8 D3[1:0] 00 D3 = 1 KV2[3:1] 100 GMOD[1:0] 00 low IMIXI 1 infra DR1I[1:0] 00 M=1 FRMT 1 high GDEM 1 low gain
Table 10-21. Country Setting New Channels (Channel 11 - 25, USA2)
Name
Setting
RA1[1:0] 01
RA2[1:0] 01 high
D1[1:0] 10 D1 = 6
D20 0 D2 = &
D3[1:0] 00 D3 = 1
KV2[3:1] 110
GMOD[1:0] 01
IMIXI 1 infra
DR1I[1:0] 00 M=1
FRMT 0 low
GDEM 1 low gain
Value
Table 10-22. Channel Frequencies and 1st LO Divider, fRef3 = 5 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 TX Channel Frequency (MHz) 46.610 46.630 46.670 46.710 46.730 46.770 46.830 46.870 46.930 46.970 RX Channel Frequency (MHz) 49.670 49.845 49.860 49.770 49.875 49.830 49.890 49.930 49.990 49.970 fLO = 1/2 fVCO3 (MHz) 38.970 39.145 39.160 39.070 39.175 39.130 39.190 39.230 39.290 39.270 DV3I[14:0] = N 7794 7829 7832 7814 7835 7826 7838 7846 7858 7854
Table 10-23. New Channel
Channel Number 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TX Channel Frequency (MHz) 43.720 43.740 43.820 43.840 43.920 43.960 44.120 44.160 44.180 44.200 44.320 44.360 44.400 44.460 44.480 RX Channel Frequency (MHz) 48.760 48.840 48.860 48.920 49.020 49.080 49.100 49.160 49.200 49.240 49.280 49.360 49.400 49.460 49.500 fLO = 1/2 fVCO3 (MHz) 38.06 38.14 38.16 38.22 38.32 38.38 38.40 38.46 38.50 38.54 38.58 38.66 38.70 38.76 38.80 DV3I[14:0] = N 7612 7628 7632 7644 7664 7676 7680 7692 7700 7708 7716 7732 7740 7752 7760
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10.11 USA Hand
Table 10-24. Country Setting Channels (Channel 1 - 10, USA1):
Name Setting Value RA1[1:0] 10 RA2[1:0] 00 max D1[1:0] 01 D1 = 8 D20 1 D2 = 8 D3[1:0] 00 D3 = 1 KV2[3:1] 100 GMOD[1:0] 00 IMIXI 0 supra DR1I[1:0] 00 M=1 FRMT 1 high GDEM 1 low gain
Table 10-25. Country Setting New Channels (Channel 11 - 25, USA2):
Name Setting Value RA1[1:0] 01 RA2[1:0] 00 high D1[1:0] 10 D1 = 6 D20 0 D2 = & D3[1:0] 00 D3 = 1 KV2[3:1] 110 GMOD[1:0] 01 IMIXI 0 supra DR1I[1:0] 00 M=1 FRMT 0 low GDEM 1 low gain
Table 10-26. Channel Frequencies and 1st LO Divider, fRef3 = 5 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 TX Channel Frequency (MHz) 49.670 49.845 49.860 49.770 49.875 49.830 49.890 49.930 49.990 49.970 RX Channel Frequency (MHz) 46.610 46.630 46.670 46.710 46.730 46.770 46.830 46.870 46.930 46.970 fLO = 1/2 fVCO3 (MHz) 57.31 57.33 57.37 57.41 57.43 57.47 57.53 57.57 57.63 57.67 DV3I[14:0] = N 11462 11466 11474 11482 11486 11494 11506 11514 11526 11534
Table 10-27. New channel
Channel Number 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TX Channel Frequency (MHz) 48.760 48.840 48.860 48.920 49.020 49.080 49.100 49.160 49.200 49.240 49.260 49.360 49.400 49.460 49.500 RX Channel Frequency (MHz) 43.720 43.740 43.820 43.840 43.920 43.960 44.120 44.160 44.180 44.200 44.320 44.360 44.400 44.460 44.480 fLO = 1/2 fVCO3 (MHz) 54.42 54.44 54.52 54.54 54.62 54.66 54.82 54.86 54.88 54.90 55.02 55.06 55.10 55.16 55.18 DV3I[14:0] = N 10884 10888 10904 10908 10924 10932 10964 10972 10976 10980 11004 11012 11020 11032 11036
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Table 10-28. USA Modulation Loop Frequencies and Dividers
N Channel 1 2 3 4 5 6 7 8 9 10 PM 13 13 13 13 13 13 13 13 13 13 QM 157 95 105 157 123 157 157 157 157 181 fMod (MHz) 7.640 7.485 7.510 7.640 7.555 7.640 7.640 7.640 7.640 7.700
Table 10-29. New Channel
N Channel 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PM 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 QM 34 10 34 18 10 2 58 50 42 34 66 50 50 50 42 fMod (MHz) 5.66 5.60 5.66 5.62 5.60 5.58 5.72 5.70 5.68 5.66 5.74 5.70 5.70 5.70 5.68
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10.12 Portugal Base
Table 10-30. Country Setting
Name Setting Value RA1[1:0] 01 RA2[1:0] 10 D1[1:0] 00 D1 = 2 D20 1 D2 = 8 D3[1:0] 11 D3 = 4 KV2[3:1] 001 GMOD[1:0] 10 IMIXI 1 infra DR1I[1:0] 11 M=4 FRMT 1 high GDEM 1 low gain
Table 10-31. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 TX Channel Frequency (MHz) 27.550 27.575 27.600 27.625 27.650 27.675 27.700 27.725 27.750 27.775 27.800 27.825 RX Channel Frequency (MHz) 37.000 37.025 37.050 37.075 37.100 37.125 37.150 37.175 37.200 37.225 37.250 37.275 fLO = 1/2 fVCO3 (MHz) 26.300 26.325 26.350 26.375 26.400 26.425 26.450 26.475 26.500 26.525 26.550 26.575 DV3I[14:0] = N 4208 4212 4216 4220 4224 4228 4232 4236 4240 4244 4248 4252
10.12.1 Portugal Modulation Loop Frequency and Divider fRef1 = 557.5 kHz/4, fMod = 1.25 MHz/4,PM = 8,QM = 216, M = 4
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10.13 Portugal Hand
Table 10-32. Country Setting
Name Setting Value RA1[1:0] 01 RA2[1:0] 01 D1[1:0] 00 D1 = 2 D20 1 D2 = 8 D3[1:0] 11 D3 = 4 KV2[3:1] 001 GMOD[1:0] 10 IMIXI 0 supra DR1I[1:0] 11 M=4 FRMT 1 high GDEM 1 low gain
Table 10-33. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 TX Channel Frequency (MHz) 37.000 37.025 37.050 37.075 37.100 37.125 37.150 37.175 37.200 37.225 37.250 37.275 RX Channel Frequency (MHz) 27.550 27.575 27.600 27.625 27.650 27.675 27.700 27.725 27.750 27.775 27.800 27.825 fLO = 1/2 fVCO3 (MHz) 38.250 38.275 38.300 38.325 38.350 38.375 38.400 38.425 38.450 38.475 38.500 38.525 DV3I[14:0] = N 6120 6124 6128 6132 6136 6140 6144 6148 6152 6156 6160 6164
10.13.1 Portugal Modulation Loop Frequency and Divider fRef1 = 557.5 kHz/4, fMod = 1.25 MHz/4,PM = 8,QM = 216, M = 4
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10.14 Taiwan Base
Table 10-34. Country Setting
Name Setting Value RA1[1:0] 10 RA2[1:0] 00 max D1[1:0] 01 D1 = 8 D20 1 D2 = 8 D3[1:0] 00 D3 = 1 KV2[3:1] 110 GMOD[1:0] 01 IMIXI 1 infra DR1I[1:0] 00 M=1 FRMT 1 high GDEM 1 low gain
Table 10-35. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 TX Channel Frequency (MHz) 45.2500 45.2750 45.3000 45.3250 45.3500 45.3750 45.4000 45.4250 45.4500 45.4750 RX Channel Frequency (MHz) 48.2500 48.2750 48.3000 48.3250 48.3500 48.3750 48.4000 48.4250 48.4500 48.4750 fLO = 1/2 fVCO3 (MHz) 37.5500 37.5750 37.6000 37.6250 37.6500 37.6750 37.7000 37.7250 37.7500 37.7750 DV3I[14:0] = N 6008 6012 6016 6020 6024 6028 6032 6036 6040 6044
10.14.1 Taiwan Modulation Loop Frequency and Divider fMod = 7.7 MHz, PM = 13,QM = 181, M = 1
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10.15 Taiwan Hand
Table 10-36. Country Setting
Name Setting Value RA1[1:0] 10 RA2[1:0] 00 max D1[1:0] 01 D1 = 8 D20 1 D2 = 8 D3[1:0] 00 D3 = 1 KV2[3:1] 110 GMOD[1:0] 00 IMIXI 0 supra DR1I[1:0] 00 M=1 FRMT 1 high GDEM 1 low gain
Table 10-37. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 TX Channel Frequency (MHz) 48.2500 48.2750 48.3000 48.3250 48.3500 48.3750 48.4000 48.4250 48.4500 48.4750 RX Channel Frequency (MHz) 45.2500 45.2750 45.3000 45.3250 45.3500 45.3750 45.4000 45.4250 45.4500 45.4750 fLO = 1/2 fVCO3 (MHz) 55.9500 55.9750 56.0000 56.0250 56.0500 56.0750 56.1000 56.1250 56.1500 56.1750 DV3I[14:0] = N 8952 8956 8960 8964 8968 8972 8976 8980 8984 8988
10.15.1 Taiwan Modulation Loop Frequency and Divider fMod = 7.7 MHz, PM = 13,QM = 181, M = 1
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10.16 China Base
Table 10-38. Country Setting
Name Setting Value RA1[1:0] 10 RA2[1:0] 00 max D1[1:0] 01 D1 = 8 D20 1 D2 = 8 D3[1:0] 00 D3 = 1 KV2[3:1] 110 GMOD[1:0] 01 IMIXI 1 infra DR1I[1:0] 00 M=1 FRMT 1 high GDEM 1 low gain
Table 10-39. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TX Channel Frequency (MHz) 45.0000 45.0250 45.0500 45.0750 45.1000 45.1250 45.1500 45.1750 45.2000 45.2250 45.2500 45.2750 45.3000 45.3250 45.3500 45.3750 45.4000 45.4250 45.4500 45.4750 RX Channel Frequency (MHz) 48.0000 48.0250 48.0500 48.0750 48.1000 48.1250 48.1500 48.1750 48.2000 48.2250 48.2500 48.2750 48.3000 48.3250 48.3500 48.3750 48.4000 48.4250 48.4500 48.4750 fLO = 1/2 fVCO3 (MHz) 37.3000 37.3250 37.3500 37.3750 37.4000 37.4250 37.4500 37.4750 37.5000 37.5250 37.5500 37.5750 37.6000 37.6250 37.6500 37.6750 37.7000 37.7250 37.7500 37.7750 DV3I[14:0] = N 5968 5972 5976 5980 5984 5988 5992 5996 6000 6004 6008 6012 6016 6020 6024 6028 6032 6036 6040 6044
10.16.1 China Modulation Loop Frequency and Divider fMod = 7.7 MHz, PM = 13,QM = 181, M = 1
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10.17 China Hand
Table 10-40. Country Setting
Name Setting Value RA1[1:0] 10 RA2[1:0] 00 max D1[1:0] 01 D1 = 8 D20 1 D2 = 8 D3[1:0] 00 D3 = 1 KV2[3:1] 110 GMOD[1:0] 00 IMIXI 0 supra DR1I[1:0] 00 M=1 FRMT 1 high GDEM 1 low gain
Table 10-41. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TX Channel Frequency (MHz) 48.000 48.0250 48.0500 48.0750 48.1000 48.1250 48.1500 48.1750 48.2000 48.2250 48.2500 48.2750 48.3000 48.3250 48.3500 48.3750 48.4000 48.4250 48.4500 48.4750 RX Channel Frequency (MHz) 45.0000 45.0250 450500 450750 45.1000 45.1250 45.1500 45.1750 45.2000 45.2250 45.2500 45.2750 45.3000 45.3250 45.3500 45.3750 45.4000 45.4250 45.4500 45.4750 fLO = 1/2 fVCO3 (MHz) 55.7000 55.7250 55.7500 55.7750 55.8000 55.8250 55.8500 55.8750 55.9000 55.9250 55.9500 55.9750 56.0000 56.0250 56.0500 56.0750 56.1000 56.1250 56.1500 56.1750 DV3I[14:0] = N 8912 8916 8920 8924 8928 8932 8936 8940 8944 8948 8952 8956 8960 8964 8968 8972 8976 8980 8984 8988
10.17.1 China Modulation Loop Frequency and Divider fMod = 7.7 MHz, PM = 13,QM = 181, M = 1
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10.18 New Zealand Base
Table 10-42. Country Setting
Name Setting Value RA1[1:0] 00 RA2[1:0] 01 D1[1:0] 11 D1 = 4 D20 1 D2 = 8 D3[1:0] 01 D3 = 2 KV2[3:1] 110 GMOD[1:0] 01 IMIXI 1 infra DR1I[1:0] 00 M=1 FRMT 0 low GDEM 1 low gain
Table 10-43. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel Number 11 12 13 14 15 16 17 18 19 20 TX Channel Frequency (MHz) 34.2500 34.2750 34.3000 34.3250 34.3500 34.3750 34.4000 34.4250 34.4500 34.4750 RX Channel Frequency (MHz) 40.2500 40.2750 40.3000 40.3250 40.3500 40.3750 40.4000 40.4250 40.4500 40.4750 fLO = 1/2 fVCO3 (MHz) 29.5500 29.5750 29.6000 29.6250 29.6500 29.6750 29.7000 29.7250 29.7500 29.7750 DV3I[14:0] = N 4728 4732 4736 4740 4744 4748 4752 4756 4760 4764
10.18.1 New Zealand Modulation Loop Frequency and Divider fMod = 4.7 MHz/4, PM = 8,QM = 96, M = 1
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10.19 New Zealand Hand
Table 10-44. Country Setting
Name Setting Value RA1[1:0] 00 max RA2[1:0] 01 min D1[1:0] 11 D1 = 4 D20 1 D2 = 8 D3[1:0] 01 D3 = 2 KV2[3:1] 101 GMOD[1:0] 01 IMIXI 0 supra DR1I[1:0] 00 M=1 FRMT 0 low GDEM 1 low gain
Table 10-45. Channel Frequencies and 1st LO Divider, fRef3 = 6.25 kHz
Channel Number 11 12 13 14 15 16 17 18 19 20 TX Channel Frequency (MHz) 40.2500 40.2750 40.3000 40.3250 40.3500 40.3750 40.4000 40.4250 40.4500 40.4750 RX Channel Frequency (MHz) 34.2500 34.2750 34.3000 34.3250 34.3500 34.3750 34.4000 34.4250 34.4500 34.4750 fLO = 1/2 fVCO3 (MHz) 44.9500 44.9750 45.0000 45.0250 45.0500 45.0750 45.1000 45.1250 45.1500 45.1750 DV3I[14:0] = N 7192 7196 7200 7204 7208 7212 7216 7220 7224 7228
10.19.1 New Zealand Modulation Loop Frequency and Divider fMod = 4.7 MHz/4, PM = 8,QM = 96, M = 1
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10.20 Korea Base
Table 10-46. Country Setting
Name Setting Value RA1[1:0] 10 RA2[1:0] 00 max D1[1:0] 01 D1 = 8 D20 1 D2 = 8 D3[1:0] 00 D3 = 1 KV2[3:1] 100 GMOD[1:0] 00 IMIXI 1 infra DR1I[1:0] 00 M=1 FRMT 1 high GDEM 1 high gain
Table 10-47. Channel Frequencies and 1st LO Divider, fRef3 = 5 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TX Channel Frequency (MHz) 46.6100 46.6300 46.6700 46.7100 46.7300 46.7700 46.8300 46.8700 46.9300 46.9700 46.5100 46.5300 46.5500 46.5700 46.5900 RX Channel Frequency (MHz) 49.6700 49.8450 49.8600 49.7700 49.8750 49.8300 49.8900 49.9300 49.9900 49.9700 49.6950 49.7100 49.7250 49.7400 49.7550 fLO = 1/2 fVCO3 (MHz) 38.9700 39.1450 39.1600 39.0700 39.1750 39.1300 39.1900 39.2300 39.2900 39.2700 39.9950 39.0100 39.0250 39.0400 39.0550 DV3I[14:0] = N 7794 7829 7832 7814 7835 7826 7838 7846 7858 7854 7799 7802 7805 7808 7811
40
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U3600BM
10.21 Korea Hand
Table 10-48. Country Setting
Name Setting Value RA1[1:0] 10 RA2[1:0] 00 max D1[1:0] 01 D1 = 8 D20 1 D2 = 8 D3[1:0] 00 D3 = 1 KV2[3:1] 100 GMOD[1:0] 00 IMIXI 0 supra DR1I[1:0] 00 M=1 FRMT 1 high GDEM 1 high gain
Table 10-49. Channel Frequencies and 1st LO Divider, fRef3 = 5 kHz
Channel Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TX Channel Frequency (MHz) 49.6700 49.8450 49.8600 49.7700 49.8750 49.8300 49.8900 49.9300 49.9900 49.9700 49.6950 49.7100 49.7250 49.7400 49.7550 RX Channel Frequency (MHz) 46.6100 46.6300 46.6700 46.7100 46.7300 46.7700 46.8300 46.8700 46.9300 46.9700 46.5100 46.5300 46.5500 46.5700 46.5900 fLO = 1/2 fVCO3 (MHz) 57.3100 57.3300 57.3700 57.4100 57.4300 57.4700 57.5300 57.5700 57.6300 57.6700 57.2100 57.2300 57.2500 57.2700 57.2900 DV3I[14:0] = N 11462 11466 11474 11482 11486 11494 11506 11514 11526 11534 11442 11446 11450 11454 11458
41
4516D-CT0-10/05
Table 10-50. Korea Modulation Loop Frequencies and Dividers
N Channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PM 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 QM 157 95 105 157 123 157 157 157 157 181 107 109 111 113 115 fMod (MHz) 7.640 7.485 7.510 7.640 7.555 7.640 7.640 7.640 7.640 7.700 7.515 7.520 7.525 7.530 7.535
Table 10-51. Crystal Specifications Drive level < 0.01 W
Parameters Load resonance frequency with 14 pF load capacitance Load capacitance Frequency tolerance Shunt capacitance Motional capacitance Series resistance Note: (1) Necessary to stay within adjustment range of oscillator FAOS (0:2) = 0 ... 5 9.2 20 -30 Symbol Min. Typ. 11.15 14 +30 3.1 Max. Unit MHz pF ppm pF fF (1)
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U3600BM
11. Ordering Information
Extended Type Number U3600BM-NFNY U3600BM-NFNG3Y Package SSO44 SSO44 Remarks Tube, Pb-free Taped and reeled, Pb-free
12. Package Information
Package SSO44
Dimensions in mm
18.05 17.80 9.15 8.65 7.50 7.30
2.35 0.3 0.8 16.8 44 23 0.25 0.10
0.25 10.50 10.20
technical drawings according to DIN specifications
1
22
43
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4516D-CT0-10/05


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